Interconnect Challenges and Carbon Nanotube as Interconnect in Nano VLSI Circuits
This chapter discusses about the behavior of Carbon Nanotube (CNT) different structures which can be used as interconnect in Very Large Scale (VLSI) circuits in nanoscale regime. Also interconnect challenges in VLSI circuits which lead to use CNT as interconnect instead of Cu, is reviewed. CNTs are...
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| Formato: | Capítulo de libro |
| Lenguaje: | inglés |
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IntechOpen
2010
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| Acceso en línea: | https://www.intechopen.com/chapters/10021 |
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| _version_ | 1879225188480974849 |
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| author | Fathi, Davood Forouzandeh, Behjat |
| author_browse | Fathi, Davood Forouzandeh, Behjat |
| author_facet | Fathi, Davood Forouzandeh, Behjat |
| author_sort | Fathi, Davood |
| building | IntechOpen |
| collection | Acceso abierto |
| description | This chapter discusses about the behavior of Carbon Nanotube (CNT) different structures which can be used as interconnect in Very Large Scale (VLSI) circuits in nanoscale regime. Also interconnect challenges in VLSI circuits which lead to use CNT as interconnect instead of Cu, is reviewed. CNTs are classified into three main types including Single-walled Carbon Nanotube (SWCNT), CNT Bundle, and Multi-walled Carbon Nanotube (MWCNT). Because of extremely high quantum resistance of a SWCNT which is about 6.45 kΩ, rope or bundle of CNTs are used which consist of parallel CNTs in order to overcome the high delay time due to the high intrinsic (quantum) resistance. Also MWCNTs which consist of parallel shells, present much less delay time with respect to SWCNTs, for the application as interconnects. In this chapter, first a short discussion about interconnect challenges in VLSI circuits is presented. Then the repeater insertion technique for the delay reduction in the global interconnects will be studied. After that, the parameters and circuit model of a CNT will be discussed. Then a brief review about the different structures of CNT interconnects including CNT bundle and MWCNT will be presented. At the continuation, the time domain behavior of a CNT bundle interconnect in a driver-CNT bundle-load configuration will be discussed and analyzed. In this analysis, CNT bundle is modeled as a transmission line circuit model. At the end, a brief study of stability analysis in CNT interconnects will be presented. |
| doi_str_mv | 10.5772/39430 |
| first_indexed | 2026-10-16T13:39:56Z |
| format | Book Chapter |
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<dc:title>Interconnect Challenges and Carbon Nanotube as Interconnect in Nano VLSI Circuits</dc:title>
<dc:creator>Davood Fathi</dc:creator>
<dc:creator>Behjat Forouzandeh</dc:creator>
<dc:subject>Physical Sciences, Engineering and Technology</dc:subject>
<dc:description>This chapter discusses about the behavior of Carbon Nanotube (CNT) different structures which can be used as interconnect in Very Large Scale (VLSI) circuits in nanoscale regime. Also interconnect challenges in VLSI circuits which lead to use CNT as interconnect instead of Cu, is reviewed. CNTs are classified into three main types including Single-walled Carbon Nanotube (SWCNT), CNT Bundle, and Multi-walled Carbon Nanotube (MWCNT). Because of extremely high quantum resistance of a SWCNT which is about 6.45 kΩ, rope or bundle of CNTs are used which consist of parallel CNTs in order to overcome the high delay time due to the high intrinsic (quantum) resistance. Also MWCNTs which consist of parallel shells, present much less delay time with respect to SWCNTs, for the application as interconnects. In this chapter, first a short discussion about interconnect challenges in VLSI circuits is presented. Then the repeater insertion technique for the delay reduction in the global interconnects will be studied. After that, the parameters and circuit model of a CNT will be discussed. Then a brief review about the different structures of CNT interconnects including CNT bundle and MWCNT will be presented. At the continuation, the time domain behavior of a CNT bundle interconnect in a driver-CNT bundle-load configuration will be discussed and analyzed. In this analysis, CNT bundle is modeled as a transmission line circuit model. At the end, a brief study of stability analysis in CNT interconnects will be presented.</dc:description>
<dc:publisher>IntechOpen</dc:publisher>
<dc:date>2010-03-01</dc:date>
<dc:type>Chapter, Part Of Book</dc:type>
<dc:identifier>https://www.intechopen.com/chapters/10021</dc:identifier>
<dc:identifier>doi:10.5772/39430</dc:identifier>
<dc:language>en</dc:language>
<dc:relation>ISBN:978-953-307-054-4</dc:relation>
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<dc:source>https://www.intechopen.com/books/3151 ; Carbon Nanotubes</dc:source>
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| id | intech-10021 |
| institution | IntechOpen |
| isbn | 978-953-307-054-4 |
| language | English |
| last_indexed | 2026-10-16T13:39:56Z |
| publishDate | 2010 |
| publishDateRange | 2010 |
| publishDateSort | 2010 |
| publisher | IntechOpen |
| publisherStr | IntechOpen |
| record_format | oai_dc |
| spelling | intech-100212010-03-01 Interconnect Challenges and Carbon Nanotube as Interconnect in Nano VLSI Circuits Davood Fathi Behjat Forouzandeh Physical Sciences, Engineering and Technology This chapter discusses about the behavior of Carbon Nanotube (CNT) different structures which can be used as interconnect in Very Large Scale (VLSI) circuits in nanoscale regime. Also interconnect challenges in VLSI circuits which lead to use CNT as interconnect instead of Cu, is reviewed. CNTs are classified into three main types including Single-walled Carbon Nanotube (SWCNT), CNT Bundle, and Multi-walled Carbon Nanotube (MWCNT). Because of extremely high quantum resistance of a SWCNT which is about 6.45 kΩ, rope or bundle of CNTs are used which consist of parallel CNTs in order to overcome the high delay time due to the high intrinsic (quantum) resistance. Also MWCNTs which consist of parallel shells, present much less delay time with respect to SWCNTs, for the application as interconnects. In this chapter, first a short discussion about interconnect challenges in VLSI circuits is presented. Then the repeater insertion technique for the delay reduction in the global interconnects will be studied. After that, the parameters and circuit model of a CNT will be discussed. Then a brief review about the different structures of CNT interconnects including CNT bundle and MWCNT will be presented. At the continuation, the time domain behavior of a CNT bundle interconnect in a driver-CNT bundle-load configuration will be discussed and analyzed. In this analysis, CNT bundle is modeled as a transmission line circuit model. At the end, a brief study of stability analysis in CNT interconnects will be presented. IntechOpen 2010-03-01 Chapter, Part Of Book https://www.intechopen.com/chapters/10021 doi:10.5772/39430 en ISBN:978-953-307-054-4 https://creativecommons.org/licenses/by-nc-sa/3.0/ https://www.intechopen.com/books/3151 ; Carbon Nanotubes |
| spellingShingle | Physical Sciences, Engineering and Technology Fathi, Davood Forouzandeh, Behjat Interconnect Challenges and Carbon Nanotube as Interconnect in Nano VLSI Circuits |
| title | Interconnect Challenges and Carbon Nanotube as Interconnect in Nano VLSI Circuits |
| title_full | Interconnect Challenges and Carbon Nanotube as Interconnect in Nano VLSI Circuits |
| title_fullStr | Interconnect Challenges and Carbon Nanotube as Interconnect in Nano VLSI Circuits |
| title_full_unstemmed | Interconnect Challenges and Carbon Nanotube as Interconnect in Nano VLSI Circuits |
| title_short | Interconnect Challenges and Carbon Nanotube as Interconnect in Nano VLSI Circuits |
| title_sort | interconnect challenges and carbon nanotube as interconnect in nano vlsi circuits |
| topic | Physical Sciences, Engineering and Technology |
| url | https://www.intechopen.com/chapters/10021 |
| work_keys_str_mv | AT fathidavood interconnectchallengesandcarbonnanotubeasinterconnectinnanovlsicircuits AT forouzandehbehjat interconnectchallengesandcarbonnanotubeasinterconnectinnanovlsicircuits |