System-Scenario Methodology to Design a Highly Reliable Radiation-Hardened Memory for Space Applications

Cache memory circuits are one of the concerns of computing systems, especially in terms of power consumption, reliability, and high performance. Voltage-scaling techniques can be used to reduce the total power consumption of the caches. However, aggressive voltage scaling significantly increases the...

Full description

Saved in:
Bibliographic Details
Main Authors: Seyedi, Azam, Kjeldsberg, Per Gunnar, Birkeland, Roger
Format: Book Chapter
Language:English
Published: IntechOpen 2023
Subjects:
Online Access:https://www.intechopen.com/chapters/88486
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Cache memory circuits are one of the concerns of computing systems, especially in terms of power consumption, reliability, and high performance. Voltage-scaling techniques can be used to reduce the total power consumption of the caches. However, aggressive voltage scaling significantly increases the probability of memory failure, especially in environments with high radiation levels, such as space. It is, therefore, important to deploy techniques to deal with reliability issues along with voltage scaling. In this chapter, we present a system-scenario methodology for radiation-hardened memory design to keep the reliability during voltage scaling. Although any SRAM array can benefit from the design, we frame our study on the recently proposed radiation-hardened cell, Nwise, which provides high level of tolerance against single event and multi event upsets in memories. To reduce the power consumption while upholding reliability, we leverage the system-scenario-based design methodology to optimize the energy consumption in applications, where system requirements vary dynamically at run time. We demonstrate the use of the methodology with a use case related to satellite systems and solar activity. Our simulations show that we achieve up to 49.3% power consumption saving compared to using a cache design with a fixed nominal power supply level.
ISBN:978-1-80355-588-1
DOI:10.5772/intechopen.113327