Perspective Chapter: Chip I/O Design Fundamentals, Methodologies and Challenges
The dramatic increase in processing power due to the combined effects of integrated circuit scaling and shifts in computer architectures from single core to multi-core systems has led to the highly scaled on-chip aggregate bandwidths to the Tb/s range. Consequently, this has resulted to the increase...
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| Autores principales: | , |
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| Formato: | Capítulo de libro |
| Lenguaje: | inglés |
| Publicado: |
IntechOpen
2024
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| Materias: | |
| Acceso en línea: | https://www.intechopen.com/chapters/89190 |
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| Sumario: | The dramatic increase in processing power due to the combined effects of integrated circuit scaling and shifts in computer architectures from single core to multi-core systems has led to the highly scaled on-chip aggregate bandwidths to the Tb/s range. Consequently, this has resulted to the increase in the amount of data transfer between chips to increase overall system performance. However, due to the limited I/O pin count in chip packages and PCBs, designing efficient high-speed and low power chip I/O is important. This chapter proposes a configurable I/O driver that can be configured between two single-ended voltage-mode drivers, a differential voltage-mode driver and a differential current-mode driver to address electronic signaling mismatches between integrated circuits for 0.4–8.0Gbps applications. Four control schemes, namely, impedance, output swing, slew rate and de-emphasis control scheme, were integrated into the configurable I/O driver to improve signal integrity by addressing the ISI, output switching noise, reflections and output swing deviation. Through the supplementary control from the four digital schemes, the proposed configurable I/O driver is capable of supporting multiple signaling types while improving high-speed signal integrity, thereby enhancing the performance of computer systems for better consumer experiences. |
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| ISBN: | 978-0-85014-339-3 |
| DOI: | 10.5772/intechopen.1004105 |