Power Reduction Using Efficient Way of Tri-State Buffer Connection
Clock gating is a very important technique for decreasing wasted power in digital design. One of the approaches to obtain dissipated power is an intention by the way of masking the clock pulse that is going to the unused part of the design. In this research, a comparative evaluation of current clock...
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| Formato: | Capítulo de libro |
| Lenguaje: | inglés |
| Publicado: |
IntechOpen
2022
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| Materias: | |
| Acceso en línea: | https://www.intechopen.com/chapters/81346 |
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